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Home > Briefs > AI startup Cerebras unveils the WSE-3, the largest chip yet for generative AI

AI startup Cerebras unveils the WSE-3, the largest chip yet for generative AI

The race for ever-larger generative artificial intelligence models continues to fuel the chip industry. On Wednesday, Cerebras Systems, one of Nvidia’s most prominent competitors, unveiled the “Wafer Scale Engine 3,” the third generation of its AI chip and the world’s largest semiconductor. Cerebras released the WSE-2 in April 2021. Its successor, the WSE-3, is designed for training AI models, meaning refining their neural weights, or parameters, to optimize their functionality before they are put into production. “It’s twice the performance, same power draw, same price, so this would be a true Moore’s Law step, and we haven’t seen that in a long time in our industry,” Cerebras co-founder and CEO Andrew Feldman said in a press briefing for the chip, referring to the decades-old rule that chip circuitry doubles roughly every 18 months. The WSE-3 doubles the rate of instructions carried out, from 62.5 petaFLOPs to 125 petaFLOPS. One petaFLOP refers to 1,000,000,000,000,000 (1 quadrillion) floating-point operations per second. The size of almost an entire 12-inch wafer, like its predecessor, the WSE-3 has shrunk its transistors from 7 nanometers — seven billionths of a meter — to 5 nanometers, boosting the transistor count from 2.6 trillion transistors in WSE-2 to 4 trillion. TSMC, the world’s largest contract chipmaker, is manufacturing the WSE-3. Cerebras has kept the same ratio of logic transistors to memory circuits by only slightly increasing the memory content of the on-chip SRAM, from 40GB to 44GB, and slightly increasing the number of compute cores from 850,000 to 900,000. “We think we’ve got the right balance now between compute and memory,” Feldman said in the briefing, which took place at the headquarters of Colovore, the startup’s cloud hosting partner, in Santa Clara, California.

Full report : AI startup Celebras’ new WSE-3 chip is the size of a single semiconductor wafer and doubles performance to handle large language models in the tens of trillions of parameters.